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ISL6261
10uA
OCSET
R ocset
OC
I phase
L
DCR
V o
Internal to
ISL6261
DROOP
VSUM
DFB
R s
C o
ESR
DROOP
1
VO
VSEN
1000pF
0~10
VCC-SENSE
To Processor
1
RTN
1000pF
VSS-SENSE
Socket Kelvin
Conections
330pF
VDIFF
FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING
I GV
C SOFT =
given in the IMVP-6 ? specification, determines the choice of
the SOFT capacitor, C SOFT , through the following equation:
(EQ. 2)
SLEWRATE
If SLEWRATE is 10mV/ μ s, and I GV is typically 200 μ A, C SOFT
Startup Operation - CLK_EN# and PGOOD
The ISL6261 provides a 3.3V logic output pin for CLK_EN#.
The system 3.3V voltage source connects to the 3V3 pin,
which powers internal circuitry that is solely devoted to the
CLK_EN# function. The output is a CMOS signal with 4mA
sourcing and sinking capability. CMOS logic eliminates the
is calculated as
C SOFT = 200 μ A ( 10 mV μ s ) = 20 nF
(EQ. 3)
need for an external pull-up resistor on this pin, eliminating
the loss on the pull-up resistor caused by CLK_EN# being
low in normal operation. This prolongs battery run time. The
= 2 . 8 mV
dV soft I ss 41 μ A
= =
μ s
Choosing 0.015 μ F will guarantee 10mV/ μ s SLEWRATE at
minimum I GV value. This choice of C SOFT controls the
startup slew rate as well. One should expect the output
voltage to slew to the Boot value of 1.2V at a rate given by
the following equation:
(EQ. 4)
dt C SOFT 0 . 015 μ F
Selecting Rbias
To properly bias the ISL6261, a reference current needs to be
derived by connecting a 147k, 1% tolerance resistor from the
RBIAS pin to ground. This provides a very accurate 10 μ A
current source from which OCSET reference current is derived.
Caution should used in layout: This resistor should be
placed in the close proximity of the RBIAS pin and be
connected to good quality signal ground. Do not connect any
other components to this pin, as they will negatively impact
the performance. Capacitance on this pin may create
instabilities and should be avoided.
16
3.3V supply should be decoupled to digital ground, not to
analog ground, for noise immunity.
At startup, CLK_EN# remains high until 20 μ s after PGD_IN
going high, and Vcc-core is regulated at the Boot voltage.
The ISL6261 triggers an internal timer for the
IMVP6_PWRGD signal (PGOOD pin). This timer allows
PGOOD to go high approximately 7ms after CLK_EN# goes
low.
Static Mode of Operation - Processor Die Sensing
Remote sensing enables the ISL6261 to regulate the core
voltage at a remote sensing point, which compensates for
various resistive voltage drops in the power delivery path.
The VSEN and RTN pins of the ISL6261 are connected to
Kelvin sense leads at the die of the processor through the
processor socket. (The signal names are Vcc_sense and
Vss_sense respectively). Processor die sensing allows the
voltage regulator to tightly control the processor voltage at
the die, free of the inconsistencies and the voltage drops due
FN9251.1
September 27, 2006
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